1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming halo implants in semiconductor devices.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase overall performance and operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase device performance and the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Moreover, there is a constant drive to increase the density of modern integrated circuit devices, i.e., to put more and more semiconductor devices, e.g., transistors, closer and closer together on a single chip. Increasing the density of integrated circuit devices makes more efficient use of the substrate plot space, and may assist in increasing the overall yield from semiconductor manufacturing operations.
One problem encountered in efforts to increase the density of modem integrated circuit devices arises from limitations of the processes used to form halo implants in semiconductor devices. By way of background, halo implants are typically formed by implanting dopant atoms into the substrate at an angle with respect to the surface of the substrate so as to result in a doped region that extends slightly under the gate dielectric of a typical field effect transistor. The dopant atoms used to form the halo implants will typically be comprised of the same type of dopant (N-type or P-type) as used to dope the underlying substrate. For example, in the case of forming NMOS devices, the halo implant will be comprised of a P-type dopant, e.g., boron. The purpose of the halo implant is to reduce the so-called short channel effects that are a result of device sizes being continually reduced. In particular, the halo implants are made in an effort to control or reduce the variations in the threshold voltage of an integrated circuit device due to variations in the channel length of the device. Despite a great effort, variations in the channel length of semiconductor devices are not uncommon. These variations occur due to a variety of reasons, e.g., manufacturing tolerances, implant variations, etc.
Many modem integrated circuit devices are comprised of both NMOS-type devices and PMOS-type devices, or a combination of both, e.g., CMOS technology. During the formation of these various halo implants, one of the types of devices, e.g., PMOS devices, must be covered or masked with a layer of material, such as photoresist, such that the dopant atoms are implanted only into the appropriate devices, i.e., the layer of photoresist keeps the dopant atoms from being implanted into unwanted areas. However, since the halo implants are typically performed at an angle, e.g., 45 degrees, the height of the layer of photoresist limits how close the devices of different construction, e.g., NMOS and PMOS devices, may be placed together. This, in turn, causes an undesirable consumption of plot space on an integrated circuit device.
FIGS. 1 and 2 illustrate the problem encountered in forming halo implants using photoresist masks on densely packed integrated circuit devices. FIG. 1 depicts a partially-formed semiconductor device 11. The device 11 is comprised of a gate dielectric 19 formed above a surface 15 of a semiconducting substrate 13, and a gate electrode 17 formed above the gate dielectric 19. A layer of photoresist 21 is formed above the gate electrode 17 and the substrate 13.
Next, as shown in FIG. 2, an opening 23 is formed in the layer of photoresist 21 using traditional photolithographic techniques. The opening 23 has relatively vertical sidewalls and relatively sharp corners 27. The problem may arise when an angled implant process, such as that indicated by arrows 29, is performed in order to introduce dopant ions into the substrate 13 under the gate dielectric 19. That is, given the relative height of the layer of photoresist, and the spacing between the sidewalls 25 of the opening 23 and the sides 31 of the electrode 17, the corner area 33 of the layer of photoresist 21 may act to prevent the ions from being implanted into the desired area, see, e.g., dashed lines 22. This is known as shadowing. Prior techniques for combating this problem included spacing devices far enough apart such that the patterned layer of photoresist 21 does not block the dopant ions from the intended target.
Moreover, the height of the photoresist mask cannot be readily reduced as existing photolithography equipment has a minimum formed thickness requirement of approximately 5000 xc3x85. Of course, it is anticipated that efforts are being made, or will be made, to reduce the minimum thickness to which layers of photoresist may be formed. However, irrespective of the thickness of the layer of photoresist 21, it is desirable to reduce the shadowing effect by the layer of photoresist during angled implantation processes, thereby allowing devices to be spaced more closely together on an integrated circuit device. This, in turn, will increase density and product yields in semiconductor device manufacturing.
The present invention is directed to a method that solves or at least reduces some or all of the aforementioned problems.
The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.